The inventions relate in general to fabricating a ferroelectric memory device. More specifically, the inventions relate to fabricating a ferroelectric memory device, in which a ferroelectric thin film is deposited by using a spin-on process.
There have been efforts made to develop a large capacity semiconductor memory device in which a ferroelectric thin film is used in a ferroelectric capacitor so that the refresh limitation of a dynamic random access memory (DRAM) can be overcome. Such a ferroelectric random access memory (xe2x80x9cFeRAMxe2x80x9d) that utilizes the ferroelectric thin film is a kind of nonvolatile memory device. This FeRAM retains the stored information even when power is removed from the device. Its operating speed is comparable to that of DRAM. Accordingly, attention is increasing turning to FeRAM as a likely candidate for a next generation memory device.
The charge storing material for this FeRAM device is a ferroelectric thin film such as, for examples, SrBi2Ta2O9 (xe2x80x9cSBTxe2x80x9d) and Pb(ZrxTi1-x)O3 (xe2x80x9cPZTxe2x80x9d). The ferroelectric thin film has two stable remnant polarizations (Pr). Thus it is formed into a thin film for use in nonvolatile memory. A nonvolatile memory device which uses ferroelectric thin film makes use of a hysteresis characteristic to store xe2x80x981sxe2x80x99 and xe2x80x980sxe2x80x99 using the remnant polarization that is present when an electric field is removed after inputting the signals by adjusting the polarization direction in the direction of the imposed electric field.
In the case where a ferroelectric thin film such as SrBi2(Ta2-xNbx)2O9 (xe2x80x9cSBTNxe2x80x9d) or (Bi4-xLax)Ti3O12 (xe2x80x9cBLTxe2x80x9d) having a layered perovskite structure is used to form a ferroelectric capacitor, there are formed upper and lower electrodes which are generally made of Pt, Ir, Ru, IrOx, RuOx, Pt-alloy or the like.
Ferroelectric thin films can be deposited several ways including: (1) spin-on method, (2) physical vapor deposition method (PVD), and (3) chemical vapor deposition method (CVD). These methods are being studied studied, but have not proven to be practical.
In general, the spin-on method has not provided sufficient conformability to the topology of the substrate, and therefore, a flattening process such as the chemical-mechanical polishing (CMP) must be carried out during the fabrication of the FeRAM.
FIG. 1 (Prior Art) illustrates the method for fabricating the FeRAM by the conventional technique.
As shown in FIG. 1 (Prior Art), a field oxide film (FOX) 12 is formed on a semiconductor substrate 11, and then, a first polysilicon layer P1 is deposited on the semiconductor substrate. Then the first polysilicon layer P1 is patterned to form a plurality of word lines 13.
Then an n-type dopant is ion-implanted into the semiconductor substrate 11 by using the word lines 13 as a mask, thereby forming a plurality of n+ sources/drains 14. Then a first interlayer dielectric film 15 is formed on the entire surface of the semiconductor substrate 11 that includes the word lines 13.
Then the first interlayer dielectric film 15 is selectively patterned to form a bit line contact hole by exposing a part of the n+ sources/drains 14. Then a second polysilicon layer P2 is deposited on the entire surface including the bit line contact hole. Then a patterning process is carried out. Thus there are formed a plurality of bit lines 16 which are electrically connected through the contact holes to the sources/drains 14.
Then a second interlayer dielectric film 17 is formed on the first interlayer dielectric film 15 including the bit lines 16. Then the second interlayer dielectric film 17 is selectively patterned to form a plug contact hole. In the region of the plug contact hole, the sources/drains 14 except the portions connected to the bit lines 16 are exposed.
Then, a third polysilicon layer P3 is deposited on the second interlayer dielectric film 17, and then, a recessing etch-back is carried out to form a polysilicon plug 18 which is buried down to a certain depth of the contact hole.
Then titanium (Ti) is deposited on the entire surface, and a heat treatment is carried out, so that reactions between Ti and Si of the polysilicon plug can be induced. Thus a Ti silicide layer 19 is formed on the polysilicon plug 18. The Ti silicide layer 19 forms an ohmic contact between the polysilicon plug 17 and a lower electrode that will be formed later.
Then a TiN layer 20 is formed on the Ti silicide layer 19. Then, the TiN layer 20 is subjected to a chemical-mechanical polishing (CMP). Then a barrier metal layer is formed to completely fill the plug contact hole and to form a stacked structure of the Ti-silicide/TiN layers 19 and 20.
Then a lower electrode 21 and a ferroelectric thin film 22 are sequentially deposited on the barrier metal layer and on the second interlayer dielectric film 17.
As described above, the high-density memory device having the COB (capacitor on bit line) structure as in the conventional technique has the following features. A capacitor is formed on the polysilicon plug 18, and during the contact etching for forming the polysilicon plug 18 in the cell region I, an aligning key region is simultaneously formed in a scribe lane region II.
Particularly, in the case where the chemical-mechanical polishing is carried out, if the polysilicon plug 18 is to be formed by a single step, then the contact hole has to have a depth of at least 10000 xc3x85. Further, when etching the plugging contact hole, the aligning key and an overlay vernier are simultaneously formed in the scribe lane region ∥. That is, there is formed a contact hole which has a depth of 10000 xc3x85 and a width of 100 xcexcMxc3x97100 xcexcm
Accordingly, the scribe lane region II is not filled during the formation of the polysilicon plug 18. In this state, the lower electrode 21 and the ferroelectric thin film 22 for the capacitor are deposited.
The lower electrode 21 is deposited generally by applying the physical vapor deposition method (PVD), and therefore, there is no problem. However, the ferroelectric thin film 22 is deposited using the spin-on method, and therefore, the thickness of the ferroelectric thin film 22 is significantly increased in the scribe lane region II.
This thick ferroelectric thin film 22 causes cracks 23 to a serious degree during a forth-coming crystallizing heat treatment, and therefore, the alignment and the overlay cannot be checked, with the result that the manufacture of the device becomes difficult.
The inventions claimed and/or described in this document overcome the above-described limitations associated with conventional techniques.
According to one aspect of the inventions, there is provided a method for fabricating a ferroelectric memory device, in which the cracking of the ferroelectric thin film is inhibited during a heat treatment in a scribe lane region (for forming an aligning key and an overlay vernier).
One of the inventive methods for fabricating a ferroelectric memory device includes: forming a transistor on a cell region of a semiconductor substrate, the semiconductor substrate including the cell region and a scribe lane region, and the transistor including a source/drain; forming a first interlayer dielectric film upon the transistor; selectively etching the first interlayer dielectric film to form a first contact hole and to expose the source/drain; forming a first conductive film on an entire surface (including the first contact hole); selectively etching the first conductive film to form a first conductive pad, the first conductive pad being connected through the first contact hole to the source/drain; forming a second interlayer dielectric film on an entire surface (including the first conductive film); selectively etching the second interlayer dielectric film to form a second contact hole and to expose the first conductive pad so as to form an aligning key region in the scribe lane region; forming a second conductive film on an entire surface (including the second contact hole); selectively etching the second conductive film to form a plug, the plug being connected through the second contact hole to the first conductive pad; and sequentially forming a lower electrode, a ferroelectric thin film and an upper electrode on the second interlayer dielectric film (including the plug).
According to another aspect of the inventions, there is provided a method for fabricating a ferroelectric memory device including: forming a transistor on a cell region of a semiconductor substrate, the semiconductor substrate including the cell region and a scribe lane region, and the transistor including a source/drain; forming a first interlayer dielectric film on an entire surface (including the transistor); selectively etching the first interlayer dielectric film to form a first contact hole and to expose a dopant junction layer; simultaneously forming a bit line and a landing pad so as to be connected through the first contact hole to the dopant junction layer; forming a second interlayer dielectric film on an entire surface (including the bit line and the landing pad); selectively etching the second interlayer dielectric film to form a second contact hole and to expose the landing pad so as to form an aligning key region in the scribe lane region; burying a stacked film of a plug and a barrier film into the second contact hole; and sequentially forming a lower electrode, a ferroelectric thin film and an upper electrode on an entire surface (including the barrier film).